The present invention relates generally to floating point processing. In particular, the present invention relates to a method for adding the input addend in an FMAC (floating-point multiply accumulate) procedure.
In the design of microprocessor architecture, three very important considerations are speed, accuracy and cost. While it is desirable to design a microprocessor (CPU) which performs multiplication, addition and other operations with superior accuracy and at a very high rate of speed, it is also desirable to design a CPU which can be cost effectively manufactured. Speed and accuracy have been greatly increased in RISC (reduced instruction set computer) CPUs by fusing multiply and add operations into the multiply accumulate operation (A*B)+C. If it is desired to merely add or multiply two numbers, the operation A*B can be performed by setting C=0, and the operation A+C can be performed by setting B=1. The component of a CPU which performs the (A*B)+C operation is commonly referred to as an FMAC (floating-point multiply accumulate unit) or MAF/FPU (multiply-add-fused floating-point unit).
The inputs to an FMAC are the operands A (multiplicand), B (multiplier) and C (addend), where A, B and C may be fixed or floating-point numbers (floating-point numbers are numbers expressed in scientific notation). The IEEE conventions for representing single-precision (32-bit), double-precision (64-bit), and extended-precision (82 bit) floating-point numbers in binary form is [S, E, M], where S is a single bit representing the sign of a number, E is a multi-bit value (e.g., 17 in extended precision) corresponding to an exponent (which may be offset by a bias), and M is a mantissa (or the fractional portion of a normalized value either stripped of or including its leading 1). (In this specification, it can be assumed that any expressed mantissa includes its leading 1.) Thus, the form of a floating-point number is S*M*2(E-bias). With single precision, M is represented by 24 bits; with double-precision, M is represented by 53 bits; and with extended precision, M is represented by 64 bits.
In carrying out the (A*B)+C operation, the FMAC initially multiplies A and B together resulting in an A*B value that is stored in a corresponding register. In most systems, a sufficiently wide data path is used for this multiplication step such that the resulting A*B mantissa has twice the bits of a single valued mantissa. For example, in an extended precision system, the A*B is normally 128 bits wide. The A*B value is then added to the C addend. With particular relevance to the present invention, a crucial step in adding these values involves adding the A*B mantissa to the C mantissa to acquire the mantissa result. U.S. Pat. No. 5,757,686 to Naffziger et al. (which is hereby expressly incorporated by reference into this specification) teaches a valuable method that minimizes the required data-path for performing this mantissa addition step.
The final step in the FMAC process is rounding the final mantissa result to the desired bit position. In extended precision, the mantissa value is rounded to 64 bits. Likewise, with double precision (DP), the value is rounded to 53 bits, and in single precision (SP), the mantissa is rounded to 24 bits. With double and single precision in register file format (which has 64 bit slots for the mantissa), the lower slots (i.e., 11 and 40, respectively) are padded with xe2x80x9c0xe2x80x9ds. Everything else that is rounded off of the resulting mantissa is discarded or used for the rounding calculation, which determines whether or not to increment or decrement the mantissa result.
In conventional rounding techniques, three values (L, G, and S) are typically used to perform the rounding calculation. The least significant bit of the result mantissa (prior to rounding) is the L value. The bit directly to the right of L is the G value, which is known as the guard bit. Everything to the right of G goes into the determination of S, which is known as the xe2x80x9csticky.xe2x80x9d The sticky is basically just an OR""ing of each of the bits to the right of G (including those that fall off, as will be addressed below). So, S is basically just a single-bit value, which is true if any bit to the right of G is 1.
FIG. 1 shows an FMAC 20 for adding the mantissa""s of A*B and C. A, B, and C 22, 24, 30, each comprising an m-bit mantissa and an exponent, and the (A*B) result 28 comprising a xe2x80x9c2m+1xe2x80x9d-bit mantissa and an exponent, is described herein. FMAC 20 generally comprise a CHI register 32, coupled to means for transferring bits of the C mantissa 30 which exceed a range of the (A*B) mantissa 28 to the Result 44; a CBUS register 36, coupled to an alignment shifter 34 for placing bits of the C mantissa 30 which overlap the range of the (A*B) mantissa 28 into the CBUS register 36, the overlapping bits contained within the (A*B) and CBUS registers 28, 36 being aligned for adding; an adder 38, coupled to the (A*B) and CBUS registers 28, 36, and providing an (A*B)+CBUS output 46; a leading bit anticipator (LBA) 40 connected to the (A*B)+CBUS output 46 of the adder 38; a normalization shifter 42, coupled to the leading bit anticipator 40, and providing a normalized temporary output 48; and means for merging those bits of the CHI register 32 comprising bits of the C mantissa 30 which exceed the range of the (A*B) mantissa 28 with one or more most significant bits of the temporary output 48 to produce an (A*B)+C accumulate output 44.
With reference to FIGS. 2-5, respectively, there are four general cases for adding the A*B and C mantissas based on the relative differences of their associated exponents. The first case is when EXP(C) is sufficiently less than EXP(AB) such that the mantissas do not overlap when being added. The second case is when EXP(C) is less than EXP(AB), but they overlap such that there is some interaction when they are added. The third case is when EXP(C) is greater than EXP(AB), but they overlap such that they interact when added. Finally, the fourth case, which is referred to as the xe2x80x9cBig Cxe2x80x9d case, occurs when EXP(C) is sufficiently larger than EXP(AB) such that they do not overlap and there is no interplay when they are added. After an (A*B) result 28 is created, the magnitude of the (A*B) 28 and C 30 exponents are compared to determine which of four possible cases exists.
FIGS. 2-5 show the adding methods for the above-described four cases. The method generally comprises the steps of comparing the exponents of (A*B) 28 and C 30 to determine whether there is an overlapping range of the (A*B) 28 and C 30 mantissas; transferring any part of the C mantissa 30 which exceeds a range of the (A*B) mantissa 28 to a CHI register 32; shifting any part of the C mantissa 30A that overlaps the range of the (A*B) mantissa 28 in the C bus 36 and zeroing out the remaining portion of C Bus 36, so as to align the bits of the (A*B) 28 and C 30 mantissas according to their respective magnitudes; if not in case 4, adding the C Bus 36 to the (A*B) mantissa 28 to generate a temporary result 46; if a portion of the C mantissa was transferred to the CHI register 32, right shifting the Temp. Result 46 such that one or more least significant bits corresponding to a number of bits transferred to the CHI register 32 out of the temporary result to generate a Shifted Temp. Result 48; and merging with a merge mask 47 the bits of the CHI register 32, which correspond to the C mantissa exceeding the A*B mantissa, with one or more most significant bit positions of the shifted temporary result 48 to generate a final accumulate result 44.
With reference to FIG. 2, case one will now be considered. In case one (FIG. 2), EXP(C) is sufficiently less than EXP(AB) such that when their exponents are compared and their mantissas aligned, there is no overlapping between AB 28 and C30. This results with no contribution from C (other than for sticky calculation) for the Final Mantissa Result 44. With C 30 being completely to the right of A*B 28, the C Bus 36 is filled with 0""s. The CHI register 32 plays no role in this case because no portion of C is higher than (falls to the left of) A*B 28. The contents of A*B register 28 and the C Bus 36 are added with the result placed in Temp Result register 46. The Temp. Result 46 and CHI 32 (which has no role in this case) are then merged together with Merge Mask 47 to produce the Final Mantissa Result 44. The values in the Merge Mask 47 are based on the difference between the AB and C exponents. The merge mask is aligned with the Temp. Result register 46 and the CHI register 32; in each bit location, it either has a 0 for selecting the corresponding CHI bit or a 1 for selecting the corresponding Temp. Result (A*B+C) bit. In this case where no portion of C falls to the left of A*B 28, the merge mask 47 has all 1""s for entirely selecting the Temp. Result register 48. Only the A*B mantissa 28 contributes to the Final Result 44, and the C mantissa 30 is used only for acquiring the sticky value.
With reference to FIG. 3, case 2 will now be described. In case two, EXP(C) is less than EXP(AB), but when properly shifted in adding alignment, a portion 30A of C overlaps with A*B 28. As with case 1, the portion 30B of C that falls off (in this case to the right) is only used for determining the sticky value and then discarded. With C 30 shifted as shown in the drawing, the C Bus 36, in its least significant portion, includes the part of C 30A that overlaps the A*B mantissa 28. The rest of the C bus 36 is filled with 0""s. For this case, the CHI register 32 again plays no role in the determination of the Final Result 44. The contents of the A*B register 28 and the C Bus 36 are then added and placed in Temp Result register 46. The Temp. Result 48 and CHI 32 are then merged together with the Merge Mask 47 to produce the Final Mantissa Result 44. Based on the exponent difference between AB and C, the merge mask again, with C being within or to the right of C, has all 1""s for entirely selecting the Temp. Result register 48 for the Final Result 44.
With reference to FIG. 4, case 3 will now be considered. A number of bits 30C of C corresponding to the difference between the C 30 and (A*B) 28 exponents are transferred into the CHI register 32 in its most significant portion. The remaining least significant portion of the CHI register 32 is filled with ones. Once the high order bits of C 30 have been transferred to CHI 32, it matters not what remains in the high order bit positions of C 30. The remaining contents of C 30 are transferred to the C Bus 36. They are shifted left a number of bits corresponding to the difference of the C 30 and (A*B) 28 exponents. It can be seen that the high order portion, 30C, of C 30 is masked from C Bus 36, and the overlapping bits, 30A, of C 30 and (A*B) 28 are aligned. The less significant bits of C Bus 36 are filled with 0""s. Having aligned the overlapping portion of C 30 with the (A*B) result 28, the Temp. result 46 is generated with the addition of A*B 28 and the C Bus 36. Sticky bit information may be used to round the Temp Result 46, and any carry out of Temp Result 46 may be used to increment CHI 32. (Note that since the less significant bits of CHI 32 are filled with ones, a carry from Temp. Result 46 will ripple through the less significant bits of CHI 32 into the bits of CHI 32 representing the high order portion of C 30.)
After obtaining Temp. Result 46, the Temp. Result 46 must be right-shifted via shifter 42 by a number of bits equal to the difference between the C 30 and (A*B) 28 exponents. The shifted Temp. result register is pictured at 48. The high order portion of C 30 contained in CHI 32 and the Shifted Temp. Result 48 are now merged with mask 47 to produce the Final Result 44. This time, based on the difference between the A*B and C exponents, the most significant bits (corresponding to the number of bits of C falling off of A*B) are now 0""s for selecting the CHI register 32, and the remaining lower bits are 1""s for selecting the Shifted Temp. Result 48.
With reference to FIG. 5, case 4 will now be addressed. This case, where C is sufficiently larger than A*B such that all of the result mantissa comes from C, is referred to as the xe2x80x9cBig Cxe2x80x9d case. As will be discussed below, the Big C case is uniquely special because when it is identified, rounding calculations can more efficiently be performed. With C 30 falling completely to the left of A*B, all of C gets put into the CHI register 32. With the Big C case being identified, the shifting and use of the C Bus can be bypassed, and CHI 32 is directly merged into the Final Mantissa Result 44. The A*B mantissa only comes into play in the sticky calculation.
In prior art, input and output precision always matched. That is, even in systems with hardware having, for example, the capability to handle double (53 bit) precision, the output may have been required to be rounded to single precision. This was not a problem, however, because with the input and output precisions being guaranteed to match, the system would know that the input precision must also be single.
FIG. 6A shows an example of this type of situation. In this example, both the input and output values are known to be single-precision floating-point numbers. The C mantissa 130 is stored in a 53 bit register, and the A*B mantissa 128 is stored in a 106 bit register. The pertinent data (mantissa) is placed on the upper portions of the operand registers, and the lower bits padded with 0""s. Thus, in the example of FIG. 6A, the upper 24 bits are the C mantissa, and the lower 29 bits are padded with 0""s. It can be seen that because that lower portion of C, which is set to 0, is the only thing overlapping with A*B, there is basically no interaction between C and A*B other than the rounding interactions. Thus, it can be identified as a case four (or Big C) case. The important thing is that it can be classified into one of the four cases and processed accordingly. Thus, in the prior art, simply by knowing the output precision, the input precision was also known, and the case threshold could be appropriately set for properly identifying a given computation""s case.
It was also a simple matter to determine L, G, and S. For example, with the Big C case, L is always a particular bit of C, i.e., the least significant bit of the mantissa. With the example of FIG. 6A, it would always be bit 30. G is always guaranteed to be 0, and sticky is just an OR""ing of A*B. If A*B is not 0, then S is true, and if it is 0, then S is false. When the Big C case is identified, it is easy to determine these values. However, in cases other than a Big C case, L, G, and S, could still be readily calculated using conventional methods for these other cases.
Thus, the above-described Naffziger algorithm, which removes the need for a 3N+1 data path width in cases 3 and 4, is an excellent algorithmxe2x80x94even when single precision values were being processed with double precision hardware. Because of that, L, G and S were easy to obtain. They were either obtained from the Big C case, or they were readily found exclusively from the Temp. Result (A*B+C) register.
Unfortunately, now, with IA64 architecture, which uses register file format (i.e., extended precision), the input and output precisions are not guaranteed to match. The input values are always in register file format. If the output is rounded to single or double precision, the lower bits on the input operands are not necessarily 0""s. Thus, when the output is to be rounded to a smaller precision, the inputs cannot be assumed to have the corresponding precision. With a reduced precision output, the lower bits only get rounded off after the addition operation is performed. Thus, case thresholds can""t be established for specific output precisionsxe2x80x94as they could in the pastxe2x80x94because, e.g., there is still interaction between the bits beyond the 24 (single precision) bits and the A*B bus. Thus, a L, G, and S can not be readily determined with the conventional algorithm by simply identifying the case. Now, rather than coming only from the Temp. Result register in determinable locations, L and G and some of sticky may come from the CHI bus. FIG. 6B shows an example that illustrates this problem. The C mantissa 170 exponent is greater than the A*B mantissa 168 exponent by 26 bits. For this case, assume that the rounding is to single precision. Thus, only 24 bits of the result mantissa will be kept. If it was known that the lower 40 bits were 0 because the number was guaranteed to be single precision, this case could be identified as a Big C case. However, there is interaction between those lower (not necessarily 0) bits and A*B.
Accordingly, what is needed is a method for obtaining the rounding parameters, L, G, and S, in an FMAC having an output precision that may be smaller than the input precision.
These and other objects, features and technical advantages are achieved by a system and method which in an m-bit precision system effectively acquires rounding parameters when the final mantissa result is rounded to a lower precision. A floating-point multiply accumulate unit is provided for performing the accumulate operation (A*B)+C. A, B, and C each comprise an m-bit mantissa and an exponent, and the (A*B) result comprises a xe2x80x9c2m+1xe2x80x9d-bit mantissa and an exponent. Also provided is a method for adding C to the (A*B) result to acquire a final mantissa result that is rounded to a first precision that is smaller than m. In one embodiment, the method includes the following acts. Comparing the exponents of (A*B) and C to determine whether there is an overlapping range of the (A*B) and C mantissas. Transferring any part of the C mantissa which exceeds a range of the (A*B) mantissa to a CHI register. Shifting any part of the C mantissa which overlaps the range of the (A*B) mantissa, so as to align the bits of the (A*B) and C mantissas according to their respective magnitudes. Adding the shifted part of the C mantissa to the (A*B) mantissa to generate a Temp. Result.
If a portion of the C mantissa was transferred to the CHI register, then shifting one or more least significant bits corresponding to a number of bits transferred to the CHI register out of the Temp. Result. Merging with a merge mask the bits of the C mantissa which were transferred to the CHI register with one or more most significant bit positions of the shifted Temp. Result to generate an accumulated 1 mantissa result. Acquiring L from a selected one of an Lbit value of the CHI register and an Lbit value of the Temp. Result based on the bit value of the merge mask corresponding to the Lbit. Finally, rounding the mantissa result to the lower precision using one or more rounding parameters including a leading bit (L).
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.